Generally, memory chips comprise an array of memory cells interconnected by bit lines and word lines. The word lines and bit lines are used to read and write binary values to each of the memory cells, wherein each memory cell represents a bit of information. Traditional memory cells typically used combinations of transistors and/or capacitors to represent each bit of information. As memory sizes are reduced, other types of memories are being developed that allow two bits of information to be stored in each memory cell.
One type of memory cell is a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory cell. Traditional SONOS memory cells are based on a transistor having a multi-layer gate electrode that uses an oxide-nitride-oxide (ONO) structure for trapping and storing charges representing a logical “1” or “0” near each of the source and drain regions, thereby storing 2 bits per cell. This type of traditional SONOS memory cell, however, does not allow for decreasing the size of the channel region, thereby limiting the size reduction of a memory cell.
Recent advancements have led to a sidewall SONOS memory cell in which charges are trapped in the nitride spacers formed alongside the gate. While this type of SONOS memory cell allows for a shorter channel length, the size of the memory cell is large due to the large active area required for the contacts between the bit lines and the source/drain regions.
For example, FIG. 1 illustrates a layout for a sidewall SONOS memory array. The SONOS memory array includes active regions 10 and 12 intersected by word lines 14 and 16, thereby forming transistors 20, 22, 24, and 26. Each transistor 20, 22, 24, and 26 has source/drain regions 30. Bit lines BL-1, BL-2, BL-3, and BL-4 are electrically coupled to either a source region or a drain region via contacts (indicated by a square with an “X” on the bit lines). As discussed above, a bit of information may be stored on both the source and drain sides of the charge-trapping nitride layer, e.g., a floating gate or a spacer.
As illustrated in FIG. 1, however, the active regions 10 and 12 must be relatively wide. The wider active regions 10 and 12 are necessitated by the need to have contacts for two bit lines, one each for the source region and the drain region. These larger active regions result in larger memory array size, thereby limiting the size reduction and scaling of the SONOS memory array.
Thus, there is the need for a memory cell layout for a SONOS-type memory array that requires less area and is more scaleable.